The present invention relates to a semiconductor device having a gate array structure in which a macro-cell is formed by a plurality of basic cells.
Generally, as a method of manufacturing a large-scale integration circuit (LSI), a gate array method is adapted for the purpose of shortening the manufacturing period.
In this method, a large number of logic gates are previously formed in a matrix fashion on a semiconductor chip, and when an order is received, electrode wirings are connected in order to complete the required logic circuit on the semiconductor chip. The wiring pattern is usually designed by a digital computer and determined by means of a grid method in which wiring routes can be selected only on lines running lengthwise and laterally in a matrix fashion, and, furthermore, lengthwise wiring routes can be selected only on the first wiring layer, lateral wiring lines can be selected only on the second wiring layer, and connections between the lines of the first and second wiring layers can be accomplished by means of through holes.
As a logic gate of the above-mentioned semiconductor device, a basic logic element, for example, a four-input NAND element, can be used, and by combining a plurality of such elements, various kinds of logic circuits usually required can be constructed. The basic element is formed as a basic cell on the semiconductor chip. For example, an AND gate can be constructed by using two basic cells, and a flip-flop circuit can be constructed by using six basic cells. Such a logic circuit which is constructed by using a plurality of basic cells which has one logic function such as AND, flip-flop, NOR, or EXCLUSIVE OR is called a macro-cell. Each macro-cell can be considered to be one element by itself, and, for example, when a flip-flop circuit is necessary for forming a logic circuit, a previously prepared macro-cell having the logic function of a flip-flop circuit may be used to form a logic circuit by forming it on the semiconductor chip as a combination of basic cells by means of a predetermined construction method.
Conventionally, when a macro-cell is constructed by means of the above-mentioned gate array method, the smallest number of basic cells necessary for the formation of the macro-cell are used. However, in the above-mentioned conventional method, there is a problem in that the density of the occupied terminals becomes so high that the computer may not discover the required wiring routes and thus the number of unconnected wiring routes may be increased. Furthermore, even if the wiring routes are discovered, these routes may be very long because they are roundabout routes on the macro-cell. When the required wiring routes are not discovered by the computer and remain unconnected, it is necessary to connect them by hand, which is troublesome and results in mis-connection and inequality. Also, when a wiring route is very long, signal transmitting time is delayed and the stray capacitance of the wiring is increased.